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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12617-1E
8-bit Proprietary Microcontrollers
CMOS
F2MC-8FX MB95100B Series
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MB95107B/F108BS/F108BW/R107B/D108BS/ MB95D108BW/FV100D-101
DESCRIPTION
The MB95100B series is general-purpose, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
FEATURE
* F2MC-8FX CPU core Instruction set optimized for controllers * Multiplication and division instructions * 16-bit arithmetic operations * Bit test branch instruction * Bit manipulation instructions etc. * Clock * Main clock * Main PLL clock * Sub clock (for dual clock product) * Sub PLL clock (for dual clock product) (Continued)
Be sure to refer to the "Check Sheet" for the latest cautions on development.
"Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Copyright(c)2006 FUJITSU LIMITED All rights reserved
MB95100B Series
(Continued) * Timer * 8/16-bit compound timer x 2 channels * 16-bit reload timer * 8/16-bit PPG x 2 channels * 16-bit PPG x 2 channels * Timebase timer * Watch prescaler (for dual clock product) * FRAM 2K bytes FRAM is loaded (MB95R107B/MB95D108BS/MB95D108BW only) * LIN-UART www..com * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * UART/SIO * Full duplex double buffer * Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable * I2C* Built-in wake-up function * External interrupt * Interrupt by edge detection (rising, falling, or both edges can be selected) * Can be used to recover from low-power consumption (standby) modes. * 8/10-bit A/D converter 8-bit or 10-bit resolution can be selected. * Low-power consumption (standby) mode * Stop mode * Sleep mode * Watch mode (for dual clock product) * Timebase timer mode * I/O port * The number of maximum ports * Single clock product : 55 ports * Dual clock product : 53 ports * Port configuration * General-purpose I/O ports (N-ch open drain) Other than MB95D108BS/MB95D108BW/MB95R107B : 6 ports MB95D108BS/MB95D108BW/MB95R107B : 4 ports * General-purpose I/O ports (CMOS) Single clock product : 49 ports Dual clock product : 47 ports * : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
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MB95100B Series
PRODUCT LINEUP
Part number MB95107B Parameter Type ROM capacity RAM capacity
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MB95F108BS/ MB95F108BW Flash memory product 60K bytes
MB95R107B*3 MASK ROM product 48K bytes
MB95D108BS/ MB95D108BW Flash memory product 60K bytes
MASK ROM product 48K bytes No
2K bytes 2K bytes No Selectable Single/Dual clock*1 Single/Dual clock*2 Selectable Single/Dual clock*1 No Number of basic instructions Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time : 136 : 8 bits : 1 to 3 bytes : 1, 8, and 16 bits : 61.5 ns (at machine clock frequency 16.25 MHz) : 0.6 s (at machine clock frequency 16.25 MHz) Single/Dual clock*2
FRAM capacity Reset output Option*4 Clock system Low voltage detection reset
CPU functions
General purpose I/O ports Timebase timer Watchdog timer Wild register Peripheral functions
* Single clock product : 55 ports (N-ch open drain *5 : 4/6 ports, CMOS : 49 ports) * Dual clock product : 53 ports (N-ch open drain *5 : 4/6 ports, CMOS : 47 ports) Interrupt cycle : 0.5 ms, 2.1 ms, 8.2 ms, 32.8 ms (at main oscillation clock 4 MHz) Reset generated cycle At main oscillation clock 10 MHz : Min 105 ms At sub oscillation clock 32.768 kHz (for dual clock product) : Min 250 ms Capable of replacing 3 bytes of ROM data Master/slave sending and receiving Bus error function and arbitration function Detecting transmitting direction function Start condition repeated generation and detection functions Built-in wake-up function Data transfer capable in UART/SIO Full duplex double buffer, Variable data length (5/6/7/8-bit), built-in baud rate generator NRZ type transfer format, error detected function LSB-first or MSB-first can be selected. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable Dedicated reload timer allowing a wide range of communication speeds to be set. Full duplex double buffer. Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable LIN functions available as the LIN master or LIN slave. 8-bit or 10-bit resolution can be selected. (Continued)
I2C
UART/SIO
LIN-UART
8/10-bit A/D converter (12 channels)
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MB95100B Series
(Continued) Part number MB95107B Parameter
MB95F108BS/ MB95F108BW
MB95R107B*3
MB95D108BS/ MB95D108BW
Two clock modes and two counter operating modes can be selected. Square wave form output 16-bit reload timer Count clock : 7 internal clocks and external clock can be selected. Counter operating mode : reload mode or one-shot mode can be selected. Each channel of the timer can be used as "8-bit timer x 2 channels" or "16-bit timer x 1 channel". 8/16-bit compound www..com Built-in timer function, PWC function, PWM function, capture function and square timer (2 channels) wave form output Count clock : 7 internal clocks and external clock can be selected. 16-bit PPG (2 channels) Peripheral functions 8/16-bit PPG (2 channels) Watch counter (for dual clock product) Watch prescaler (for dual clock product) External interrupt (12 channels) PWM mode or one-shot mode can be selected. Counter operating clock : Eight selectable clock sources Support for external trigger start Each channel of the PPG can be used as "8-bit PPG x 2 channels" or "16-bit PPG x 1 channel". Counter operating clock : Eight selectable clock sources Count clock : Four selectable clock sources (125 ms, 250 ms, 500 ms, or 1 s) Counter value can be set from 0 to 63. (Capable of counting for 1 minute when selecting clock source 1 second and setting counter value to 60) 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) Interrupt by edge detection (rising, falling, or both edges can be selected.) Can be used to recover from standby modes. Supports automatic programming, Embedded AlgorithmTM *6 Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Number of write/erase cycles (Minimum) : 10000 times Data retention time : 20 years Erase can be performed on each block Boot block configuration Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash Sleep, stop, watch (for dual clock product), and timebase timer
Flash memory
Standby mode
*1 : Specify clock mode when ordering MASK ROM. *2 : MB95F108BS/MB95D108BS is single clock and MB95F108BW/MB95D108BW is dual clock. *3 : This device is under development. *4 : For details of option, refer to " MASK OPTION". *5 : MB95D108BS/D108BW/R107B contain 4 general-purpose I/O ports for N-ch open drain. Port number other than MB95D108BS/D108BW/R107B has 6 general-purpose I/O ports for N-ch open drain. *6 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. Note : Part number of the evaluation products in MB95100B series is MB95FV100D-101. When using it, the MCU board (MB2146-301A) is required.
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MB95100B Series
SELECT OF OSCILLATION STABILIZATION WAIT TIME (MASK ROM PRODUCT ONLY)
For the MASK ROM product, you can set the mask option when ordering MASK ROM to select the initial value of main clock oscillation stabilization wait time from among the following four values. Note that the evaluation and Flash memory products are fixed their initial value of main clock oscillation stabilization wait time at the maximum value. Select of oscillation stabilization wait time (2 - 2) /FCH
2
Remarks 0.5 s (at main oscillation clock 4 MHz) Approx. 1.02 ms (at main oscillation clock 4 MHz) Approx. 2.05 ms (at main oscillation clock 4 MHz) Approx. 4.10 ms (at main oscillation clock 4 MHz)
(212 - 2) /FCH
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(213 - 2) /FCH (2 - 2) /FCH
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PACKAGES AND CORRESPONDING PRODUCTS
Part number Package FPT-64P-M03 FPT-64P-M09 BGA-224P-M08 : Available : Unavailable MB95107B MB95R107B MB95F108BS/F108BW MB95D108BS/D108BW MB95FV100D-101
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MB95100B Series
DIFFERENCES AMONG PRODUCTS AND NOTES ON SELECTING PRODUCTS
* Notes on Using Evaluation Products The evaluation product has not only the functions of the MB95100B series but also those of other products to support software development for multiple series and models of the F2MC-8FX family. The I/O addresses for peripheral resources not used by the MB95100B series are therefore access-barred. Read/write access to these access-barred addresses may cause peripheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. Particularly, do not use word access to odd numbered byte address in the prohibited areas (If these access are used, the address may be read or written unexpectedly). Also, www..com as the read values of prohibited addresses on the evaluation product are different to the values on the Flash memory and MASK ROM products, do not use these values in the program.
The evaluation product do not support the functions of some bits in single-byte registers. Read/write access to these bits does not cause hardware malfunctions. The evaluation, Flash memory, and MASK ROM products are designed to behave completely the same way in terms of hardware and software. * Difference of Memory Spaces If the amount of memory on the evaluation product is different from that of the Flash memory or MASK ROM product, carefully check the difference in the amount of memory from the model to be actually used when developing software. For details of memory space, refer to " CPU CORE". * Current Consumption The current consumption of Flash memory product is greater than for MASK ROM product. For details of current consumption, refer to " ELECTRICAL CHARACTERISTICS". * Package For details of information on each package, refer to " PACKAGES AND CORRESPONDING PRODUCTS" and " PACKAGE DIMENSIONS". * Operating voltage The operating voltage are different among the evaluation, Flash memory, and MASK ROM products. For details of operating voltage, refer to " ELECTRICAL CHARACTERISTICS". * Difference between RST and MOD pins The input type of RST and MOD pins is CMOS input on the Flash memory product. The RST and MOD pins are hysteresis inputs on the MASK ROM product. A pull - down resistor is provided for the MOD pin of the MASK ROM product.
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MB95100B Series
PIN ASSIGNMENT
(TOP VIEW)
AVss P30/AN00 P31/AN01 P32/AN02 P33/AN03 P34/AN04 P35/AN05 P36/AN06 P37/AN07 P40/AN08 P41/AN09 P42/AN10 P43/AN11 P67/SIN P66/SOT P65/SCK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
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AVcc AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0 P70/TO0 MOD X0 X1 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P64/EC1 P63/TO11 P62/TO10 P61/PPG11 P60/PPG10 P53/TRG1 P52/PPG1 P51/SDA0*2 P50/SCL0*2 P24/EC0 P23/TO01 P22/TO00 P21/PPG01 P20/PPG00 P14/PPG0 P13/TRG0/ADTG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. *2 : P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW.
Vcc PG0 PG2/X1A*1 PG1/X0A*1 RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 P11/UO0 P12/UCK0
(FPT-64P-M03, FPT-64P-M09)
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MB95100B Series
PIN DESCRIPTION
Pin no. 1 2 3 4
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Pin name AVCC AVR PE3/INT13 PE2/INT12 PE1/INT11 PE0/INT10 P83 P82 P81 P80 P71/TI0
I/O circuit type*
Function A/D converter power supply pin A/D converter reference input pin
P
General-purpose I/O port The pins are shared with the external interrupt input.
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
O
General-purpose I/O port
H P70/TO0 MOD X0 X1 VSS VCC PG0 PG2/X1A H/A PG1/X0A RST P00/INT00 P01/INT01 P02/INT02 P03/INT03 P04/INT04 P05/INT05 P06/INT06 P07/INT07 P10/UI0 G C B' B A H
General-purpose I/O port. The pin is shared with 16 - bit reload timer ch.0 input. General-purpose I/O port. The pin is shared with 16 - bit reload timer ch.0 output. An operating mode designation pin Main clock input oscillation pin Main clock input/output oscillation pin Power supply pin (GND) Power supply pin General-purpose I/O port. Single-system product is general-purpose port (PG2). Dual-system product is sub clock input/output oscillation pin (32 kHz). Single-system product is general-purpose port (PG1). Dual-system product is sub clock input oscillation pin (32 kHz). Reset pin
General-purpose I/O port. The pins are shared with external interrupt input. Large current port.
General-purpose I/O port. The pin is shared with UART/SIO ch.0 data input. (Continued)
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MB95100B Series
Pin no. 31 32
Pin name P11/UO0 P12/UCK0 P13/TRG0/ ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0
I/O circuit type*
Function General-purpose I/O port. The pin is shared with UART/SIO ch.0 data output. General-purpose I/O port. The pin is shared with UART/SIO ch.0 clock I/O.
H
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33
General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 trigger input (TRG0) and A/D converter trigger input (ADTG). General-purpose I/O port. The pin is shared with 16-bit PPG ch.0 output. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.0 output.
34 35 36 37 38 39
H
General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.0 output. General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.0 clock input. General-purpose I/O port (Except MB95R107B , MB95D108BS, and MB95D108BW) . The pin is shared with I2C ch.0 clock I/O. General-purpose I/O port (Except MB95R107B, MB95D108BS, and MB95D108BW) . The pin is shared with I2C ch.0 data I/O. General-purpose I/O port. The pin is shared with 16-bit PPG ch.1 output. General-purpose I/O port. The pin is shared with 16-bit PPG ch.1 trigger input. General-purpose I/O port. The pins are shared with 8/16-bit PPG ch.1 output. General-purpose I/O port. The pins are shared with 8/16-bit compound timer ch.1 output.
40
P50/SCL0 I
41
P51/SDA0
42 43 44 45 46 47 48 49 50 51
P52/PPG1 H P53/TRG1 P60/PPG10 P61/PPG11 P62/TO10 P63/TO11 P64/EC1 P65/SCK P66/SOT P67/SIN L K
General-purpose I/O port. The pin is shared with 8/16-bit compound timer ch.1 clock input. General-purpose I/O port. The pin is shared with LIN-UART clock I/O. General-purpose I/O port. The pin is shared with LIN-UART data output. General-purpose I/O port. The pin is shared with LIN-UART data input. (Continued)
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MB95100B Series
(Continued) Pin no. 52 53 54 55 56
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Pin name P43/AN11 P42/AN10 P41/AN09 P40/AN08 P37/AN07 P36/AN06 P35/AN05 P34/AN04 P33/AN03 P32/AN02 P31/AN01 P30/AN00 AVSS
I/O circuit type*
Function
J
General-purpose I/O port. The pins are shared with A/D converter analog input.
57 58 59 60 61 62 63 64
J
General-purpose I/O port. The pins are shared with A/D converter analog input.
A/D converter power supply pin (GND)
* : For the I/O circuit type, refer to " I/O CIRCUIT TYPE".
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MB95100B Series
I/O CIRCUIT TYPE
Type Circuit Remarks * Oscillation circuit * High-speed side Feedback resistance value : approx. 1 M * Low-speed side Feedback resistance : approx. 24 M (Evaluation product : approx. 10 M) Dumping resistance : approx. 144 k (Evaluation product : without dumping resistance) * Only for input Hysteresis input only for MASK ROM product With pull-down resistor only for MASK ROM product * Hysteresis input only for MASK ROM product B' Reset input * CMOS output * Hysteresis input
X1 (X1A) X0 (X0A) N-ch
Clock input
A
Standby control
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B
Mode input
R
P-ch
Digital output Digital output Hysteresis input
C Standby control
External interrupt enable
N-ch
R P-ch P-ch
Pull-up control Digital output Digital output CMOS input Hysteresis input
* * * *
CMOS output CMOS input Hysteresis input With pull-up control
G
N-ch
Standby control
R P-ch P-ch
Pull-up control Digital output Digital output Hysteresis input
* CMOS output * Hysteresis input * With pull-up control
H
N-ch
Standby control
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MB95100B Series
Type
Circuit * * * Digital output * CMOS input Hysteresis input * * Pull-up control * Digital output * Digital output
N-ch
Remarks N-ch open drain output CMOS input Hysteresis input P-ch transistor is existed in MB95D108BS, MB95D108BW, and MB95R107B.
P-ch
I
N-ch
Standby control
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R P-ch P-ch
CMOS output Hysteresis input Analog input With pull-up control
J
Analog input A/D control Standby control
P-ch
Hysteresis input * CMOS output Digital output * Hysteresis input Digital output Hysteresis input
P-ch
K Standby control
N-ch
L
N-ch
* CMOS output Digital output * CMOS input * Hysteresis input Digital output CMOS input Hysteresis input * N-ch open drain output Digital output * Hysteresis input Hysteresis input (Continued)
Standby control
O Standby control
N-ch
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MB95100B Series
(Continued) Type
R P-ch P-ch
Circuit Pull-up control Digital output Digital output Hysteresis input
Remarks * CMOS output * Hysteresis input * With pull-up control
P
N-ch
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Standby control External interrupt control
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MB95100B Series
HANDLING DEVICES
* Preventing Latch-up Care must be taken to ensure that maximum voltage ratings are not exceeded when they are used. Latch-up may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between VCC pin and VSS pins. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. Also, take care to prevent the analog power supply voltage (AVCC , AVR) and analog input voltage from exceeding the digital power supply voltage (VCC) when the analog system power supply is turned on or off.
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* Stable Supply Voltage Supply voltage should be stabilized. A sudden change in power-supply voltage may cause a malfunction even within the guaranteed operating range of the VCC power-supply voltage. For stabilization, in principle, keep the variation in VCC ripple (p-p value) in a commercial frequency range (50/60 Hz) not to exceed 10% of the standard VCC value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 V/ms during a momentary change such as when the power supply is switched. * Precautions for Use of External Clock Even when an external clock is used, oscillation stabilization wait time is required for power-on reset, wake-up from sub clock mode or stop mode.
PIN CONNECTION
* Treatment of Unused Pin Leaving unused input pins unconnected can cause abnormal operation or latch-up, leaving to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/ output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is an unused output pin, make it open. * Treatment of Power Supply Pins on A/D Converter Connect to be AVCC = VCC and AVSS = AVR = VSS even if the A/D converter is not in use. Noise riding on the AVCC pin may cause accuracy degradation. So, connect approx. 0.1 F ceramic capacitor as a bypass capacitor between AVCC and AVSS pins in the vicinity of this device. * Power Supply Pins In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS pins near this device.
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MB95100B Series
* Mode Pin (MOD) Connect the MOD pin directly to VCC or VSS pins. To prevent the device unintentionally entering the test mode due to noise, lay out the printed circuit board so as to minimize the distance from the MOD pin to VCC or VSS pin and to provide a low-impedance connection. * Analog Power Supply Always set the same potential to AVCC and VCC pins. When VCC > AVCC, the current may flow through the AN00 to AN11 pins.
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for Use of FRAM
When the device is connected to I2C external pins (SCL0 and SDA0) , the device with the same slave addresses (1010000B to 1010111B) as built-in FRAM cannot be used. When built-in FRAM is used without connecting the device to I2C external pins, external pull-up resistor (1.1k or more) should be connected to SCL0 and SDA0 pins. P50 and P51 cannot be used in MB95R107B , MB95D108BS, and MB95D108BW.
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MB95100B Series
PROGRAMMING FLASH MEMORY MICROCONTROLLERS USING PARALLEL PROGRAMMER
* Supported Parallel Programmers and Adapters The following table lists supported parallel programmers and adapters. Package Applicable adapter model FPT-64P-M03 FPT-64P-M09
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Parallel programmers
TEF110-108F35AP TEF110-108F36AP
AF9708 (Ver 02.35G or more) AF9709/B (Ver 02.35G or more) AF9723+AF9834 (Ver 02.08E or more)
Note : For information on applicable adapter models and parallel programmers, contact the following: Support Group, Inc. TEL: +81-53-428-8380 The individual sectors of Flash memory correspond to addresses used for CPU access and programming by the parallel programmer as follows: Flash memory SA1 (4K bytes) SA2 (4K bytes) 2FFFH 3000H SA3 (4K bytes) 3FFFH 4000H SA4 (16K bytes) 7FFFH 8000H SA5 (16K bytes) BFFFH C000H SA6 (4K bytes) CFFFH D000H SA7 (4K bytes) DFFFH E000H SA8 (4K bytes) EFFFH F000H SA9 (4K bytes) FFFFH 7FFFFH *: Programmer addresses are corresponding to CPU addresses, used when the parallel programmer programs data into Flash memory. These programmer addresses are used for the parallel programmer to program or erase data in Flash memory. * Programming Method 1) Set the type code of the parallel programmer to 17226. 2) Load program data to parallel programmer addresses 71000H to 7FFFFH. 3) Programmed by parallel programmer 7EFFFH 7F000H 7DFFFH 7E000H 7CFFFH 7D000H 7BFFFH 7C000H
Upper bank Lower bank
* Sector Configuration
CPU address 1000H 1FFFH 2000H
Programmer address* 71000H 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H
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MB95100B Series
BLOCK DIAGRAM
F MC-8FX CPU RST X0,X1 PG2/X1A*1 PG1/X0A*1
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2
Reset control Clock control Watch prescaler Watch counter
External interrupt ch.0 to ch.7
ROM RAM Interrupt control Wild register
PG0
P00/INT00 to P07/INT07 P10/UI0 P11/UO0 P12/UCK0
16-bit PPG ch.1
P52/PPG1 P53/TRG1 P60/PPG10 P61/PPG11 P62/TO10
UART/SIO
8/16-bit PPG ch.1 Internal bus
P13/TRG0/ADTG P14/PPG0 P20/PPG00 P21/PPG01 P22/TO00 P23/TO01 P24/EC0
16-bit PPG ch.0
8/16-bit compound timer ch.1
P63/TO11 P64/EC1 P65/SCK
8/16-bit PPG ch.0
LIN-UART 8/16-bit compound timer ch.0 16-bit reload timer
P66/SOT P67/SIN P70/TO0 P71/TI0 P80 to P83
P30/AN00 to P37/AN07 P40/AN08 to P43/AN11 AVCC AVSS AVR P50/SCL0*2 P51/SDA0*2 I 2C 8/10-bit A/D converter
External interrupt ch.8 to ch.11
PE0/INT10 to PE3/INT13
FRAM*3 Port Other pins MOD, VCC, VSS Port
*1 : Single clock product is general-purpose port, and dual clock product is sub clock oscillation pin. *2 : P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW. *3 : MB95R107B, MB95D108BS, and MB95D108BW only
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MB95100B Series
CPU CORE
1. Memory space
Memory space of the MB95100B series is 64 Kbytes and consists of I/O area, data area, and program area. The memory space includes special-purpose areas such as the general-purpose registers and vector table. Memory map of the MB95100B series is shown below. * Memory Map
MB95F108BS MB95F108BW MB95D108BS MB95D108BW 0000H I/O 0080H RAM 2 Kbytes 0080H I/O RAM 2 Kbytes 0000H I/O 0080H RAM 3.75 Kbytes 0100H Register 0200H Access prohibited Extended I/O 1000H Access prohibited Flash memory 60 Kbytes MASK ROM 48 Kbytes FFFFH FFFFH FFFFH Flash memory 60 Kbytes 0F80H Extended I/O 1000H
MB95107B MB95R107B
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MB95FV100D-101
0000H
0100H Register 0200H 0880H 0F80H Extended I/O 1000H Access prohibited
0100H Register 0200H 0880H 0F80H
4000H
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MB95100B Series
2. Register
The MB95100B series has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The dedicated registers are as follows: Program counter (PC) : A 16-bit register to indicate locations where instructions are stored Accumulator (A) : A 16-bit register for temporary storage of arithmetic operations. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator. In the case of an 8-bit data processing instruction, the lower 1 byte is used. Index register (IX) : A 16-bit register for index modification Extra pointer (EP) : A 16-bit pointer to point to a memory address www..com Stack pointer (SP) : A 16-bit register to indicate a stack area Program status (PS) : A 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register
16-bit
PC A T IX EP SP PS
Initial Value : Program counter : Accumulator : Temporary accumulator : Index register : Extra pointer : Stack pointer : Program status FFFDH 0000H 0000H 0000H 0000H 0000H 0030H
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and a direct bank pointer (DP) and the lower 8 bits for use as a condition code register (CCR) . (Refer to the diagram below.) * Structure of the program status
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 PS R4 R3 R2 R1 R0 DP2 DP1 bit 8 DP0 bit 7 H bit 6 I bit 5 IL1 bit 4 IL0 bit 3 N bit 2 Z bit 1 V bit 0 C
RP
DP
CCR
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MB95100B Series
The RP indicates the address of the register bank currently being used. The relationship between the content of RP and the real address conforms to the conversion rule illustrated below: * Rule for Conversion of Actual Addresses in the General-purpose Register Area RP upper
"0" "0" "0" "0" "0" "0" "0" "1" A8 R4 A7 R3 A6 R2 A5 R1 A4 R0 A3
OP code lower
b2 A2 b1 A1 b0 A0
Generated address A15 A14 A13 A12 A11 A10 A9
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The DP specifies the area for mapping instructions (16 different instructions such as MOV A, dir) using direct addresses to 0080H to 00FFH. Direct bank pointer (DP2 to DP0) Specified address area Mapping area XXXB (no effect to mapping) 000B (initial value) 001B 010B 011B 100B 101B 110B 111B 0080H to 00FFH 0000H to 007FH 0000H to 007FH (without mapping) 0080H to 00FFH (without mapping) 0100H to 017FH 0180H to 01FFH 0200H to 027FH 0280H to 02FFH 0300H to 037FH 0380H to 03FFH 0400H to 047FH
The CCR consists of the bits indicating arithmetic operation results or transfer data contents and the bits that control CPU operations at interrupt. H flag : Set to "1" when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. This flag is for decimal adjustment instructions. I flag : Interrupt is enabled when this flag is set to "1". Interrupt is disabled when this flag is set to "0". The flag is cleared to "0" when reset. IL1, IL0 : Indicates the level of the interrupt currently enabled. Processes an interrupt only if its request level is higher than the value indicated by these bits. IL1 0 0 1 1 N flag Z flag V flag C flag IL0 0 1 0 1 Interrupt level 0 1 2 3 Low = no interruption Priority High
: Set to "1" if the MSB is set to "1" as the result of an arithmetic operation. Cleared to "0" when the
bit is set to "0". : Set to "1" when an arithmetic operation results in "0". Cleared to "0" otherwise. : Set to "1" if the complement on 2 overflows as a result of an arithmetic operation. Cleared to "0" otherwise. : Set to "1" when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to "0" otherwise. Set to the shift-out value in the case of a shift instruction.
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MB95100B Series
The following general-purpose registers are provided: General-purpose registers: 8-bit data storage registers The general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8register. Up to a total of 32 banks can be used on the MB95100B series. The bank currently in use is specified by the register bank pointer (RP), and the lower 3 bits of OP code indicates the general-purpose register 0 (R0) to general-purpose register 7 (R7). * Register Bank Configuration
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8-bit
1F8H
This address = 0100H + 8 x (RP)
Address 100H R0 R1 R2 R3 R4 R5 R6 107H R7 Bank 0 R0 R1 R2 R3 R4 R5 R6 R7
R0 R1 R2 R3 R4 R5 R6 1FFH R7 Bank 31
32 banks 32 banks (RAM area) The number of banks is limited by the usable RAM capacitance.
Memory area
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MB95100B Series
FRAM
* Slave address of FRAM
FRAM operates as one of the slave devices connected to the I2C, and the I2C is used to read from or write to FRAM. When data is transferred by the I2C, the slave address of FRAM is shown below.
Slave address (7 bits) Slave ID (4 bits) Page select bit* (3 bits) 000B : page 0 001B : page 1 010B : page 2 011B : page 3 100B : page 4 101B : page 5 110B : page 6 111B : page 7
R/W bit (1 bit)
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0
1
0
0 : at write 1 : at read
* : Page select bit : Set the value corresponding to the accessed page * Memory configuration of FRAM The capacitance of the built-in FRAM is 2 Kbytes. The memory configuration of FRAM consists of 8 pages as follows. The capacitance of each page is 256 bytes. Page Address Capacitance 0 1 2 3 4 5 6 7 00H to FFH 00H to FFH 00H to FFH 00H to FFH 00H to FFH 00H to FFH 00H to FFH 00H to FFH 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes 256 bytes
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MB95100B Series
* Single byte write
Start Condition Microcontroller MSB S FRAM LSB A MSB Address LSB A MSB Data Byte LSB A P Address & Data Stop Condition
Slave Address 0
Acknowledge
* Compound byte write www..com
Start Condition Microcontroller S FRAM MSB LSB A Address & Data MSB Address LSB A MSB Data Byte LSB A MSB Data Byte Stop Condition LSB AP
Slave Address 0
Acknowledge
* Current address read
Start Condition Address Microcontroller S FRAM MSB LSB A MSB Data Byte LSB 1 P No Acknowledge Stop Condition
Slave Address 1
Acknowledge
Data
* Continuous address read
Microcontroller Start Condition Address MSB S FRAM LSB A MSB Data Byte Acknowledge LSB A MSB Data Byte No Acknowledge Stop Condition LSB 1P
Slave Address 1
Acknowledge
Data
* Select (random) read
Start Condition Address Microcontroller MSB LSB MSB S Slave Address 0 A FRAM Acknowledge Data Start Condition Address LSB MSB LSB MSB A S Slave Address 1 A No Acknowledge Acknowledge LSB MSB A LSB 1P Data Byte Data Byte Stop Condition
Address
Notes : * When the device is connected to I2C external pins (SCL0 and SDA0) , the device with the same addresses (1010000B to 1010111B) as built-in FRAM cannot be used. * When FRAM is used without connecting the device built into the pull-up resistor to I2C external pins, external pull-up resistor (1.1 k or more) should be connected to SCL0 and SDA0 pins. * P50 and P51 cannot be used in MB95R107B, MB95D108BS, and MB95D108BW. 23
MB95100B Series
I/O MAP
Address 0000H 0001H 0002H 0003H 0004H
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Register abbreviation PDR0 DDR0 PDR1 DDR1 WATR PLLC SYCC STBC RSRR TBTC WPCR WDTC PDR2 DDR2 PDR3 DDR3 PDR4 DDR4 PDR5 DDR5 PDR6 DDR6 PDR7 DDR7 PDR8 DDR8 PDRE DDRE PDRG
Register name Port 0 data register Port 0 direction register Port 1 data register Port 1 direction register (Disabled) Oscillation stabilization wait time setting register PLL control register System clock control register Standby control register Reset source register Timebase timer control register Watch prescaler control register Watchdog timer control register (Disabled) Port 2 data register Port 2 direction register Port 3 data register Port 3 direction register Port 4 data register Port 4 direction register Port 5 data register Port 5 direction register Port 6 data register Port 6 direction register Port 7 data register Port 7 direction register Port 8 data register Port 8 direction register (Disabled) Port E data register Port E direction register (Disabled) Port G data register
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00000000B 00000000B 11111111B 00000000B 1010X011B 00000000B XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH to 0025H 0026H 0027H 0028H, 0029H 002AH
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MB95100B Series
Address 002BH 002CH 002DH 002EH 002FH 0030H www..com 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH 0040H, 0041H 0042H 0043H 0044H 0045H 0046H, 0047H 0048H 0049H 004AH 004BH 004CH 004DH
Register abbreviation DDRG PUL1 PUL2 PUL3 PUL4 PUL5 PUL7 PULE PULG T01CR1 T00CR1 T11CR1 T10CR1 PC01 PC00 PC11 PC10 TMCSRH0 TMCSRL0 PCNTH0 PCNTL0 PCNTH1 PCNTL1 EIC00 EIC10 EIC20 EIC30 EIC01 EIC11
Register name Port G direction register (Disabled) Port 1 pull - up register Port 2 pull - up register Port 3 pull - up register Port 4 pull - up register Port 5 pull - up register Port 7 pull - up register (Disabled) Port E pull - up register Port G pull - up register 8/16-bit compound timer 01 control status register 1 ch.0 8/16-bit compound timer 00 control status register 1 ch.0 8/16-bit compound timer 11 control status register 1 ch.1 8/16-bit compound timer 10 control status register 1 ch.1 8/16-bit PPG1 control register ch.0 8/16-bit PPG0 control register ch.0 8/16-bit PPG1 control register ch.1 8/16-bit PPG0 control register ch.1 16-bit reload timer control status register (Upper byte) ch.0 16-bit reload timer control status register (Lower byte) ch.0 (Disabled) 16-bit PPG control status register (Upper byte) ch.0 16-bit PPG control status register (Lower byte) ch.0 16-bit PPG control status register (Upper byte) ch.1 16-bit PPG control status register (Lower byte) ch.1 (Disabled) External interrupt circuit control register ch.0/ch.1 External interrupt circuit control register ch.2/ch.3 External interrupt circuit control register ch.4/ch.5 External interrupt circuit control register ch.6/ch.7 External interrupt circuit control register ch.8/ch.9 External interrupt circuit control register ch.10/ch.11
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued) 25
MB95100B Series
Address 004EH, 004FH 0050H 0051H 0052H
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Register abbreviation SCR SMR SSR RDR/TDR ESCR ECCR SMC10 SMC20 SSR0 TDR0 RDR0 IBCR00 IBCR10 IBSR0 IDDR0 IAAR0 ICCR0 ADC1 ADC2 ADDH ADDL WCSR FSR SWRE0 SWRE1 WREN WROR
2
Register name (Disabled) LIN-UART serial control register LIN-UART serial mode register LIN-UART serial status register LIN-UART reception/transmission data register LIN-UART extended status control register LIN-UART extended communication control register UART/SIO serial mode control register 1 ch.0 UART/SIO serial mode control register 2 ch.0 UART/SIO serial status register ch.0 UART/SIO serial output data register ch.0 UART/SIO serial input data register ch.0 (Disabled) I2C bus control register 0 ch.0 I2C bus control register 1 ch.0 I2C bus status register ch.0 I C data register ch.0 I C address register ch.0 I2C clock control register ch.0 (Disabled) 8/10-bit A/D converter control register 1 8/10-bit A/D converter control register 2 8/10-bit A/D converter data register (Upper byte) 8/10-bit A/D converter data register (Lower byte) Watch counter status register (Disabled) Flash memory status register Flash memory sector writing control register 0 Flash memory sector writing control register 1 (Disabled) Wild register address compare enable register Wild register data test setting register
2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 00000000B 00000000B 00001000B 00000000B 00000100B 000000XXB 00000000B 00100000B 00000001B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 000X0000B 00000000B 00000000B 00000000B 00000000B (Continued)
0053H 0054H 0055H 0056H 0057H 0058H 0059H
005AH 005BH to 005FH 0060H 0061H 0062H 0063H 0064H 0065H 0066H to 006BH 006CH 006DH 006EH 006FH 0070H 0071H 0072H 0073H 0074H 0075H 0076H 0077H
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MB95100B Series
Address 0078H 0079H 007AH 007BH 007CH
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Register abbreviation ILR0 ILR1 ILR2 ILR3 ILR4 ILR5 WRARH0 WRARL0 WRDR0 WRARH1 WRARL1 WRDR1 WRARH2 WRARL2 WRDR2 T01CR0 T00CR0 T01DR T00DR TMCR0 T11CR0 T10CR0 T11DR T10DR TMCR1 PPS01 PPS00 PDS01 PDS00
Register name Mirror of register bank pointer (RP) and direct bank pointer (DP) Interrupt level setting register 0 Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Interrupt level setting register 4 Interrupt level setting register 5 (Disabled) Wild register address setting register (Upper byte) ch.0 Wild register address setting register (Lower byte) ch.0 Wild register data setting register ch.0 Wild register address setting register (Upper byte) ch.1 Wild register address setting register (Lower byte) ch.1 Wild register data setting register ch.1 Wild register address setting register (Upper byte) ch.2 Wild register address setting register (Lower byte) ch.2 Wild register data setting register ch.2 (Disabled) 8/16-bit compound timer 01 control status register 0 ch.0 8/16-bit compound timer 00 control status register 0 ch.0 8/16-bit compound timer 01 data register ch.0 8/16-bit compound timer 00 data register ch.0 8/16-bit compound timer 00/01 timer mode control register ch.0 8/16-bit compound timer 11 control status register 0 ch.1 8/16-bit compound timer 10 control status register 0 ch.1 8/16-bit compound timer 11 data register ch.1 8/16-bit compound timer 10 data register ch.1 8/16-bit compound timer 10/11 timer mode control register ch.1 8/16-bit PPG1 cycle setting buffer register ch.0 8/16-bit PPG0 cycle setting buffer register ch.0 8/16-bit PPG1 duty setting buffer register ch.0 8/16-bit PPG0 duty setting buffer register ch.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 11111111B 11111111B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B (Continued) 27
007DH 007EH 007FH 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H to 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH
0F9CH 0F9DH 0F9EH 0F9FH
MB95100B Series
Address 0FA0H 0FA1H 0FA2H 0FA3H 0FA4H 0FA5H www..com 0FA6H 0FA7H 0FA8H, 0FA9H 0FAAH 0FABH 0FACH 0FADH 0FAEH 0FAFH 0FB0H 0FB1H 0FB2H 0FB3H 0FB4H 0FB5H 0FB6H to 0FBBH 0FBCH 0FBDH 0FBEH 0FBFH 0FC0H, 0FC1H 0FC2H 0FC3H
Register abbreviation PPS11 PPS10 PDS11 PDS10 PPGS REVC TMRH0/ TMRLRH0 TMRL0/ TMRLRL0 PDCRH0 PDCRL0 PCSRH0 PCSRL0 PDUTH0 PDUTL0 PDCRH1 PDCRL1 PCSRH1 PCSRL1 PDUTH1 PDUTL1 BGR1 BGR0 PSSR0 BRSR0 AIDRH AIDRL
Register name 8/16-bit PPG1 cycle setting buffer register ch.1 8/16-bit PPG0 cycle setting buffer register ch.1 8/16-bit PPG1 duty setting buffer register ch.1 8/16-bit PPG0 duty setting buffer register ch.1 8/16-bit PPG start register 8/16-bit PPG output inversion register 16-bit timer register (Upper byte) ch.0/ 16-bit reload register (Upper byte) ch.0 16-bit timer register (Lower byte) ch.0/ 16-bit reload register (Lower byte) ch.0 (Disabled) 16-bit PPG down counter register (Upper byte) ch.0 16-bit PPG down counter register (Lower byte) ch.0 16-bit PPG cycle setting buffer register (Upper byte) ch.0 16-bit PPG cycle setting buffer register (Lower byte) ch.0 16-bit PPG duty setting buffer register (Upper byte) ch.0 16-bit PPG duty setting buffer register (Lower byte) ch.0 16-bit PPG down counter register (Upper byte) ch.1 16-bit PPG down counter register (Lower byte) ch.1 16-bit PPG cycle setting buffer register (Upper byte) ch.1 16-bit PPG cycle setting buffer register (Lower byte) ch.1 16-bit PPG duty setting buffer register (Upper byte) ch.1 16-bit PPG duty setting buffer register (Lower byte) ch.1 (Disabled) LIN-UART baud rate generator register 1 LIN-UART baud rate generator register 0 UART/SIO dedicated baud rate generator prescaler select register ch.0 UART/SIO dedicated baud rate generator baud rate setting register ch.0 (Disabled) A/D input disable register (Upper byte) A/D input disable register (Lower byte)
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 11111111B 11111111B 11111111B 11111111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B (Continued)
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MB95100B Series
(Continued) Address 0FC4H to 0FE2H 0FE3H 0FE4H to 0FEDH 0FEEH 0FEFH 0FF0H to 0FFFH Register abbreviation WCDR ILSR WICR Register name (Disabled) Watch counter data register (Disabled) Input level select register Interrupt pin control register (Disabled) R/W R/W R/W R/W Initial value 00111111B 00000000B 01000000B
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* R/W access symbols R/W : Readable/Writable R : Read only W : Write only * Initial value symbols 0 : The initial value of this bit is "0". 1 : The initial value of this bit is "1". X : The initial value of this bit is undefined. Note : Do not write to the " (Disabled) ". Reading the " (Disabled) " returns an undefined value.
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MB95100B Series
INTERRUPT SOURCE TABLE
Interrupt source External interrupt ch.0 External interrupt ch.4 External interrupt ch.1
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Interrupt request number IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20
Vector table address Upper FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFDEH FFDCH FFDAH FFD8H FFD6H FFD4H FFD2H Lower FFFBH FFF9H FFF7H FFF5H FFF3H FFF1H FFEFH FFEDH FFEBH FFE9H FFE7H FFE5H FFE3H FFE1H FFDFH FFDDH FFDBH FFD9H FFD7H FFD5H FFD3H
Same level Bit name of priority order interrupt level (at simultaneous setting register occurrence) L00 [1 : 0] L01 [1 : 0] L02 [1 : 0] L03 [1 : 0] L04 [1 : 0] L05 [1 : 0] L06 [1 : 0] L07 [1 : 0] L08 [1 : 0] L09 [1 : 0] L10 [1 : 0] L11 [1 : 0] L12 [1 : 0] L13 [1 : 0] L14 [1 : 0] L15 [1 : 0] L16 [1 : 0] L17 [1 : 0] L18 [1 : 0] L19 [1 : 0] L20 [1 : 0] High
External interrupt ch.5 External interrupt ch.2 External interrupt ch.6 External interrupt ch.3 External interrupt ch.7 UART/SIO ch.0 8/16-bit compound timer ch.0 (Lower) 8/16-bit compound timer ch.0 (Upper) LIN-UART (reception) LIN-UART (transmission) 8/16-bit PPG ch.1 (Lower) 8/16-bit PPG ch.1 (Upper) 16-bit reload timer ch.0 8/16-bit PPG ch.0 (Upper) 8/16-bit PPG ch.0 (Lower) 8/16-bit compound timer ch.1 (Upper) 16-bit PPG ch.0 I2C ch.0 16-bit PPG ch.1 8/10-bit A/D converter Timebase timer Watch timer/Watch counter External interrupt ch.8 External interrupt ch.9 External interrupt ch.10 External interrupt ch.11 8/16-bit compound timer ch.1 (Lower) Flash memory
IRQ21
FFD0H
FFD1H
L21 [1 : 0]
IRQ22 IRQ23
FFCEH FFCCH
FFCFH FFCDH
L22 [1 : 0] L23 [1 : 0] Low
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MB95100B Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC AVCC AVR
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Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.0 + 2.0 20 15 15
Unit *2 *2 V V mA mA mA
Remarks
Power supply voltage*
1
V
Input voltage*1 Output voltage*1 Maximum clamp current Total maximum clamp current "L" level maximum output current
VI1 VI2 VO ICLAMP |ICLAMP| IOL1 IOL2
Other than P80 to P83*3 P80 to P83 *3 Applicable to pins*4 Applicable to pins*4 Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin)
IOLAV1 "L" level average current IOLAV2
4 mA 12
"L" level total maximum output current "L" level total average output current "H" level maximum output current
IOL IOLAV IOH1 IOH2

100
mA Total average output current = operating current x operating ratio (Total of pins) Other than P00 to P07 P00 to P07 Other than P00 to P07 Average output current = operating current x operating ratio (1 pin) P00 to P07 Average output current = operating current x operating ratio (1 pin)
50 - 15 - 15 -4
mA
mA
IOHAV1 "H" level average current IOHAV2
mA -8
"H" level total maximum output current "H" level total average output current
IOH IOHAV

- 100 - 50
mA Total average output current = operating current x operating ratio (Total of pins) (Continued) 31
mA
MB95100B Series
(Continued) Parameter Power consumption Operating temperature Symbol Pd TA Rating Min - 40 - 55 Storage temperature
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Max 320 + 85 + 150
Unit mW C C
Remarks
TSTG - 40 + 125
MB95107B, MB95F108BS, MB95F108BW MB95R107B, MB95D108BS, MB95D108BW
*1 : The parameter is based on AVSS = VSS = 0.0 V. *2 : Apply equal potential to AVCC and VCC. AVR should not exceed AVCC + 0.3 V. *3 : VI1 and Vo should not exceed VCC + 0.3 V. VI1 must not exceed the rating voltage. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI1 rating. *4 : Applicable to pins : P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P70, P71, PE0 to PE3, PG0 * Use within recommended operating conditions. * Use at DC voltage (current). * The + B signal is an input signal that exceeds VCC voltage. The + B signal should always be applied a limiting resistance placed between the + B signal and the microcontroller. * The value of the limiting resistance should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this affects other devices. * Note that if the + B signal is inputted when the microcontroller power supply is off (not fixed at 0 V), the power supply is provided from the pins, so that incomplete operation may result. * Note that if the + B input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the + B input pin open. * Sample recommended circuits : * Input/Output Equivalent circuits Protective diode Limiting resistance
Vcc P-ch N-ch R
+ B input (0 V to 16 V)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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MB95100B Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter SymPin name Condition bol Value Min 1.8* Max 3.3 Unit Remarks At normal operating, Flash memory product, TA = -10 C to +85 C At normal operating, MASK ROM product, TA = -10 C to +85 C At normal operating, Flash memory product, TA = -40 C to +85 C At normal operating, MASK ROM product, TA = -40 C to +85 C V 2.7 3.3 At normal operating, Flash memory product, At FRAM access, TA = -40 C to +85 C At normal operating, MASK ROM product, At FRAM access, TA = -40 C to +85 C MB95FV100D-101 TA = + 5 C to +35 C Retain status in stop mode, Flash memory product Retain status in stop mode, MASK ROM product V C
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1.8*
3.6
2.0*
3.3
Power supply voltage VCC, AVCC
2.0*
3.6
2.7
3.6
A/D converter reference input voltage Operating temperature AVR TA

2.6 1.5 1.5
3.6 3.3 3.6
1.8 - 40
AVCC + 85
* : The values vary with the operating frequency. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB95100B Series
3. DC Characteristics
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol VIH1 Pin name P10, P67 Conditions *1 Value Min 0.7 VCC Typ Max VCC + 0.3 Unit V Remarks At selecting CMOS input level At selecting CMOS input level MB95F108BS, MB95F108BW, MB95107B, MB95FV100D-101 At selecting CMOS input level MB95D108BS, MB95D108BW, MB95R107B
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VIH2 P50, P51 0.7 VCC
VSS + 5.5 V
VCC + 0.3
VIHS1 "H" level input voltage
P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P52, P53, P60 to P67, P70, P71, PE0 to PE3, PG0, PG1*2, PG2*2 P80 to P83
*1
0.8 VCC
VCC + 0.3
V
Hysteresis input
VIHS2
*1
0.8 VCC
VSS + 5.5
V
Hysteresis input Hysteresis input MB95F108BS, MB95F108BW, MB95107B, MB95FV100D-101 Hysteresis input MB95D108BS, MB95D108BW, MB95R107B
VIHS3 P50, P51 0.8 VCC
VSS + 5.5 V VSS + 5.0
VIHM RST, MOD
0.7 VCC
VCC + 0.3
V
CMOS input (Flash memory product) Hysteresis input (MASK ROM product) (Continued)
0.8 VCC
VCC + 0.3
V
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MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol VIL Pin name P10, P50, P51, P67 P00 to P07, P10 to P14, P20 to P24, P30 to P37, P40 to P43, P50 to P53, P60 to P67, P70, P71, P80 to P83, PE0 to PE3, PG0, PG1*2, PG2*2 Conditions Value Min VSS - 0.3 Typ Max 0.3 VCC Unit Remarks At selecting CMOS input level (Hysteresis input)
*1
V
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VILS "L" level input voltage
*1
VSS - 0.3
0.2 VCC
V
Hysteresis input
VILM RST, MOD Input leakage current (Hi-Z output leakage current) "H" level output voltage "L" level output voltage Port other than P50, P51, P80 to P83
VSS - 0.3
0.3 VCC
V
CMOS input (Flash memory product) Hysteresis input (MASK ROM product) When the pull-up is prohibition setting
VSS - 0.3
0.2 VCC
V
ILI
0.0 V < VI < VCC
-5
+5
A
VOH1
Output pin other IOH = - 4.0 mA than P00 to P07 IOH = - 8.0 mA Output pin other IOL = 4.0 mA than P00 to P07 IOL = 12 mA P80 to P83
2.4 2.4 VSS - 0.3

0.4 0.4 VSS + 5.5 VSS + 5.5
V V V V MB95F108BS, MB95F108BW, MB95107B MB95D108BS, MB95D108BW, MB95R107B A (Continued)
VOH2 P00 to P07 VOL1
VOL2 P00 to P07 VD1
Open-drain output application voltage
VD2
P50, P51
VSS - 0.3
VCC + 0.3
V
Open-drain output leakage current
ILIOD
P50, P51, P80 to P83
0.0 V < VI < VSS + 5.5 V
5
35
MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks
P10 to P14, P20 to P24, P30 to P37, P40 to P43, VI = 0.0 V Pull-up resistor RPULL P52, P53, P70, P71, PE0 to PE3, www..com PG0, PG1*2, PG2*2 Pull-down resistor Input capacitance RMOD MOD CIN VI = VCC
25
50
100
k
When the pull-up is permission setting
25
50 5
100 15
k pF
MASK ROM product
Other than AVCC, f = 1 MHz AVSS, AVR, VCC, VSS
FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2)
11.0
14.0
MB95F108BS, MB95F108BW mA (at other than Flash memory writing and erasing) MB95F108BS, MB95F108BW mA (at Flash memory writing and erasing) mA MB95107B MB95F108BS, MB95F108BW mA (at other than Flash memory writing and erasing) MB95F108BS, MB95F108BW mA (at Flash memory writing and erasing) mA MB95107B MB95D108BS, MB95D108BW mA (at other than Flash memory writing and erasing) MB95D108BS, MB95D108BW mA (at Flash memory write and erase) mA MB95R107B (Continued)

30.0
35.0
7.3
10.0
Power supply current*3 ICC FCH = 32 MHz VCC (External clock FMP = 16 MHz operation) Main clock mode (divided by 2)
17.6
22.4

38.1
44.9
11.7
16.0
FCH = 20 MHz FMP = 10 MHz Main clock mode (divided by 2) When FRAM read and write (fSCL = 400 kHz)
11.1
15.0

30
35
7.4
11.0
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MB95100B Series
(VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions Value Min Typ Max Unit Remarks
ICC
www..com
FCH = 32 MHz FMP = 16 MHz Main clock mode (divided by 2) When FRAM read and write (fSCL = 400 kHz)
17.7
22.5
MB95D108BS, MB95D108BW mA (at other than Flash memory writing and erasing) MB95D108BS, MB95D108BW mA (at Flash memory write and erase) mA MB95R107B

38.1
44.9
11.8
16.1
ICCS
FCH = 20 MHz FMP = 10 MHz Main Sleep mode (divided by 2) FCH = 32 MHz FMP = 16 MHz Main Sleep mode (divided by 2) VCC (External clock operation) FCL = 32 kHz FMPL = 16 kHz Sub clock mode (divided by 2) , TA = + 25 C FCL = 32 kHz FMPL = 16 kHz Sub sleep mode (divided by 2) , TA = + 25 C FCL = 32 kHz Watch mode Main stop mode TA = + 25 C FCH = 4 MHz FMP = 10 MHz Main PLL mode (multiplied by 2.5) FCH = 6.4 MHz FMP = 16 MHz Main PLL mode (multiplied by 2.5)
4.5
6.0
mA
7.2
9.6
mA
Power supply current*3
ICCL
25
35
A
ICCLS
7
15
A

2 1 10 6.7 16.0 10.8
10 5 14 10.0 22.4 16.0
A
ICCT
Flash memory product
A MASK ROM product mA Flash memory product
mA MASK ROM product mA Flash memory product
ICCMPLL
mA MASK ROM product (Continued)
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MB95100B Series
(Continued) (VCC = AVCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Symbol Pin name Conditions FCL = 32 kHz FMPL = 128 kHz Sub PLL mode (multiplied by 4) , TA = + 25 C VCC (External FCH = 10 MHz clock operation) Timebase timer mode TA = + 25 C Sub stop mode TA = + 25 C FCH = 10 MHz At operating of A/D conversion AVCC IAH FCH = 10 MHz At stopping of A/D conversion TA = + 25 C Value Min Typ Max Unit Remarks
ICCSPLL
190
250
A
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ICTS Power supply current*3
0.4
0.5
mA
ICCH

1
5
A mA
IA
1.3
2.2
1
5
A
*1 : P10, P50, P51, and P67 can switch the input level to either the "CMOS input level" or "hysteresis input level". The switching of the input level can be set by the input level selection register (ILSR). *2 : Single clock product only *3 : Power supply current is regulated by external clock. * Refer to "4. AC characteristics (1) Clock Timing" for FCH and FCL. * Refer to "4. AC characteristics (2) Source Clock/Machine Clock" for FMP and FMPL.
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MB95100B Series
4. AC Characteristics
(1) Clock Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter SymPin name Conditions bol Value Min 1.00 1.00
www..com
Typ 32.768
Max
Unit
Remarks When using main oscillation circuit
16.25 MHz
32.50 MHz When using external clock 10.00 MHz Main PLL multiplied by 1 8.13 6.50 4.06 MHz Main PLL multiplied by 2 MHz Main PLL multiplied by 2.5 MHz Main PLL multiplied by 4 kHz When using sub oscillation circuit
FCH
X0, X1
3.00 3.00 3.00
Clock frequency
3.00 FCL X0A, X1A 61.5 30.8 tLCYL tWH1 tWL1 tWH2 tWL2 tCR tCF X0A, X1A 61.5
32.768
When using sub PLL Flash memory product : kHz VCC = 2.3 V to 3.3 V MASK ROM product : VCC = 2.3 V to 3.6 V ns ns s ns s ns When using main oscillation circuit When using external clock When using sub oscillation circuit, When using external clock When using external clock, duty ratio is about 30% to 70%. When using external clock
tHCYL Clock cycle time
X0, X1
30.5 15.2
1000 1000 10
X0 X0A X0, X0A
Input clock pulse width
Input clock rise time and fall time
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MB95100B Series
* Input wave form for using external clock (main clock)
tHCYL tWH1 tCR tCF 0.8 VCC 0.8 VCC 0.2 VCC
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tWL1
X0
0.2 VCC
0.2 VCC
* Figure of main clock Input port external connection When using a crystal or ceramic oscillator
Microcontroller X0 X1 FCH C1 C2
When using external clock
Microcontroller X0 X1
Open
FCH
* Input wave form for using external clock (sub clock)
tLCYL tWH2 tCR tCF 0.8 VCC 0.8 VCC 0.1 VCC 0.1 VCC 0.1 VCC tWL2
X0A
* Figure of sub clock input port external connection When using a crystal or ceramic oscillator
Microcontroller X0A X1A FCL C1 C2
When using external clock
Microcontroller X0A X1A
Open
FCL
40
MB95100B Series
(2) Source Clock/Machine Clock Parameter Sym- Pin bol name Value Min 61.5 tSCLK 7.6 FSP FSPL 0.5 16.384 100 tMCLK 7.6 FMP FMPL 0.031 1.024 976.5 16.250 s 61.0 16.25 s Typ Max 2000
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Unit Remarks When using main clock Min : FCH = 8.125 MHz, PLL multiplied by 2 Max : FCH = 1 MHz, divided by 2 When using sub clock Min : FCL = 32 kHz, PLL multiplied by 4 Max : FCL = 32 kHz, divided by 2
Source clock cycle time*1 (Clock before setting division)
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ns
Source clock frequency Machine clock cycle time*2 (Minimum instruction execution time) Machine clock frequency
MHz When using main clock When using main clock Min : FSP = 16.25 MHz, no division Max : FSP = 0.5 MHz, divided by 16 When using sub clock Min : FSPL = 131 kHz, no division Max : FSPL = 16 kHz, divided by 16
131.072 kHz When using sub clock 32000 ns
MHz When using main clock
131.072 kHz When using sub clock
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) . This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) , and it becomes the machine clock. Further, the source clock can be selected as follow. * Main clock divided by 2 * PLL multiplication of main clock (select from 1, 2, 2.5, 4 multiplication) * Sub clock divided by 2 * PLL multiplication of sub clock (select from 2, 3, 4 multiplication) *2 : Operation clock of the microcontroller. Machine clock can be selected as follow. * Source clock (no division) * Source clock divided by 4 * Source clock divided by 8 * Source clock divided by 16
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MB95100B Series
* Outline of clock generation block
FCH (main oscillation) Divided by 2
Main PLL x1 x2 x 2.5 x4
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SCLK (source clock) Divided by 2 Clock mode select bit (SYCC: SCS1, SCS0)
FCL (sub oscillation)
Division circuit x1 x 1/4 x 1/8 x 1/16
MCLK (machine clock)
Sub PLL x2 x3 x4
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MB95100B Series
* Operating voltage - Operating frequency (When TA = - 10 C to + 85 C) * MB95107B, MB95R107B Sub PLL operation guarantee range Sub clock mode and watch mode
3.6 3.6
FRAM operating guarantee range Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
www..com
Operating voltage (V)
2.7
2.3
1.8
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
5 MHz
16.25 MHz
PLL operation
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
* MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range
3.3 3.3
FRAM operating guarantee range Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
Operating voltage (V)
2.7
2.3
1.8
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
7.5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
43
MB95100B Series
* Operating voltage - Operating frequency (When TA = - 40 C to + 85 C) * MB95107B, MB95R107B Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range
3.6 3.6
FRAM operating guarantee range Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
www..com
Operating voltage (V)
2.7
2.3
1.8
1.8
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz 5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
* MB95F108BS, MB95F108BW, MB95D108BS, MB95D108BW Sub PLL operation guarantee range Sub clock mode and watch mode operation guarantee range
3.3 3.3
FRAM operating guarantee range Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
Operating voltage (V)
2.7
2.3 2.0
2.0
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz 5 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
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MB95100B Series
* Operating voltage - Operating frequency (TA = + 5 C to + 35 C) * MB95FV100D-101 Sub PLL, Sub clock mode and watch mode operation guarantee range
3.6 3.6
FRAM, Main clock mode and main PLL mode operation guarantee range Operating voltage (V)
Operating voltage (V)
3.3
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2.6
2.6
16.384 kHz
32 kHz
131.072 kHz
0.5 MHz 3 MHz
10 MHz
16.25 MHz
PLL operation guarantee range
PLL operation guarantee range Main clock operation guarantee range
Source clock frequency (FSPL)
Source clock frequency (FSP)
45
MB95100B Series
* Main PLL operation frequency
[MHz] 16.25 16
15
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x4
12
x 2.5 Source clock frequency (Fsp)
10
x2
x1
7.5
6
5
3
0
3
4 4.062
5
6.4 6.5
8 8.125
10 [MHz]
Machine clock frequency (FMP)
46
MB95100B Series
(3) External Reset (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter RST "L" level pulse width Symbol Value Min 2 tMCLK*1 tRSTL Oscillation time of oscillator*2 + 2 tMCLK*1 Max Unit ns ns Remarks At normal operating At stop mode, sub clock mode, sub sleep mode, and watch mode
*1 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
www..com *2 : Oscillation
start time of oscillator is the time that the amplitude reaches 90 %. In the crystal oscillator, the oscillation time is between several ms and tens of ms. In ceramic oscillators, the oscillation time is between hundreds of s and several ms. In the external clock, the oscillation time is 0 ms.
* At normal operating
tRSTL
RST
0.2 VCC 0.2 VCC
* At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
tRSTL 0.2 VCC 0.2 VCC
RST
90% of amplitude
X0
Internal operating clock
2 tMCLK
Oscillation time Oscillation stabilization wait time of oscillator Execute instruction Internal reset
47
MB95100B Series
(4) Power-on Reset (AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Power supply rising time Power supply cutoff time Symbol tR tOFF Conditions Value Min 1 Max 36 Unit ms ms Waiting time until power-on Remarks
Note : The power supply must be turned on within the selected oscillation stabilization time.
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tR 1.5 V
tOFF
VCC
0.2 V
0.2 V
0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power supply voltages during operation, set the slope of rising within 20 mV/ms as shown below.
VCC
1.5 V
Limiting the slope of rising within 20 mV/ms is recommended. Hold Condition in stop mode
VSS
48
MB95100B Series
(5) Peripheral Input Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Peripheral input "H" pulse width Peripheral input "L" pulse width Symbol
tILIH tIHIL
Pin name INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1
Value Min 2 tMCLK* 2 tMCLK* Max
Unit ns ns
www..com
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tILIH
tIHIL
INT00 to INT07, INT10 to INT13, EC0, EC1, TI0, TRG0/ADTG, TRG1
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
49
MB95100B Series
(6) UART/SIO, Serial I/O Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Serial clock cycle time UCK UO time Valid UI UCK UCK valid UI hold time
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Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Pin name UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0 UCK0 UCK0 UCK0, UO0 UCK0, UI0 UCK0, UI0
Conditions
Value Min 4 tMCLK* - 190 2 tMCLK* 2 tMCLK* 4 tMCLK* 4 tMCLK* 0 2 tMCLK* 2 tMCLK* Max + 190 190
Unit ns ns ns ns ns ns ns ns ns
Internal clock operation output pin : CL = 80 pF + 1TTL.
Serial clock "H" pulse width Serial clock "L" pulse width UCK UO time
Valid UI UCK UCK valid UI hold time
External clock operation output pin : CL = 80 pF + 1TTL.
* : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
* Internal shift clock mode
tSCYC
UCK0
2.4 V 0.8 V tSLOV 0.8 V
UO0
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
UI0
0.8 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tSLOV
UCK0
UO0
2.4 V 0.8 V tIVSH tSHIX 0.8 VCC 0.2 VCC
UI0
0.8 VCC 0.2 VCC
50
MB95100B Series
(7) LIN-UART Timing Sampling at the rising edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time
www..comSINSCK Valid
SymPin name bol tSCYC tSLOVI tIVSHI tSHIXI tSLSH tSHSL tIVSHE tSHIXE tF tR SCK
Conditions
Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 2 tMCLK* + 95
3
Unit ns ns ns ns ns ns ns ns ns ns ns
SCK valid SIN hold time Serial clock "L" pulse width Serial clock "H" pulse width SCK SOT delay time Valid SINSCK SCK valid SIN hold time SCK fall time SCK rise time
Internal clock SCK, SOT operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK External clock SCK, SIN operation output pin : CL = 80 pF + 1 TTL. SCK, SIN SCK SCK
0 3 tMCLK*3 - tR tMCLK* + 95
3
tSLOVE SCK, SOT
190 tMCLK*3 + 95
10 10
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
51
MB95100B Series
* Internal shift clock mode
tSCYC 2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 V
SCK
SOT
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SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSLSH tSHSL 0.8 VCC 0.2 VCC tF tSLOVE 2.4 V 0.8 V tIVSHE tSHIXE 0.2 VCC tR 0.8 VCC
SCK
0.8 VCC
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
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MB95100B Series
Sampling at the falling edge of sampling clock*1 and prohibited serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 0) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SINSCK
www..com SCK
Symbol tSCYC tSHOVI tIVSLI tSLIXI tSHSL tSLSH tSHOVE tIVSLE tSLIXE tF tR
Pin name SCK SCK, SOT
Conditions
Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 2 tMCLK* + 95
3
Unit ns ns ns ns ns ns ns ns ns ns ns
valid SIN hold time
Internal clock operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK, SIN SCK SCK
0 3 tMCLK*3 - tR tMCLK*3 + 95 190 tMCLK*3 + 95
Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SINSCK SCK valid SIN hold time SCK fall time SCK rise time
SCK, SOT
External clock SCK, SIN operation output pin : SCK, SIN CL = 80 pF + 1 TTL. SCK SCK
10 10
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
53
MB95100B Series
* Internal shift clock mode
tSCYC
SCK
2.4 V 0.8 V tSHOVI 2.4 V 0.8 V tIVSLI tSLIXI
2.4 V
SOT
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SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
* External shift clock mode
tSHSL tSLSH 0.8 VCC 0.2 VCC tSHOVE 2.4 V 0.8 V tIVSLE tSLIXE tF 0.2 VCC
SCK
0.2 VCC tR
0.8 VCC
SOT
SIN
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
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MB95100B Series
Sampling at the rising edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 0, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SINSCK
www..com SCK
Symbol tSCYC tSHOVI tIVSLI tSLIXI tSOVLI
Pin name SCK SCK, SOT SCK, SIN SCK, SIN SCK, SOT
Conditions
Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 4 tMCLK*3
Unit ns ns ns ns ns
valid SIN hold time
Internal clock operation output pin : CL = 80 pF + 1 TTL.
0
SOTSCK delay time
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tSCYC
SCK
0.8 V tSOVLI 2.4 V 0.8 V tIVSLI
2.4 V
tSHOVI
2.4 V 0.8 V tSLIXI 0.8 VCC 0.2 VCC
0.8 V
SOT
SIN
0.8 VCC 0.2 VCC
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MB95100B Series
Sampling at the falling edge of sampling clock*1 and enabled serial clock delay*2 (ESCR register : SCES bit = 1, ECCR register : SCDE bit = 1) (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter Serial clock cycle time SCKSOT delay time Valid SINSCK
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Symbol tSCYC tSLOVI tIVSHI tSHIXI tSOVHI
Pin name SCK SCK, SOT
Conditions
Value Min 5 tMCLK*3 -95 tMCLK* + 190
3
Max + 95 4 tMCLK*3
Unit ns ns ns ns ns
valid SIN hold time
Internal clock SCK, SIN operating output pin : CL = 80 pF + 1 TTL. SCK, SIN
0
SOTSCK delay time
SCK, SOT
*1 : Provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : Serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : Refer to " (2) Source Clock/Machine Clock" for tMCLK.
tSCYC
SCK
tSOVHI
2.4 V 0.8 V tSLOVI 2.4 V 0.8 V tIVSHI tSHIXI 0.8 VCC 0.2 VCC 2.4 V 0.8 V
2.4 V
SOT
SIN
0.8 VCC 0.2 VCC
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MB95100B Series
(8) I2C Timing (VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Value Parameter SCL clock frequency (Repeat) Start condition hold time SDA SCL
www..com SCL clock
Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF
Pin name SCL0 SCL0 SDA0 SCL0 SCL0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0
Conditions
Standard-mode Min 0 4.0 4.7 4.0 4.7 Max 100 3.45*2
Fast-mode Min 0 0.6 1.3 0.6 0.6 0 0.1 0.6 1.3 Max 400 0.9*3
Unit kHz s s s s s s s s
"L" width
SCL clock "H" width (Repeat) Start condition setup time SCL SDA Data hold time SCL SDA Data setup time SDA SCL Stop condition setup time SCL SDA Bus free time between stop condition and start condition
R = 1.7 k, C = 50 pF*1
0 0.25 4 4.7
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : The maximum tHD;DAT have only to be met if the device dose not stretch the "L" width (tLOW) of the SCL signal. *3 : A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met.
tWAKEUP SDA0 tLOW SCL0 tHD;STA tSU;DAT tSU;STA tSU;STO tHD;DAT tHIGH tHD;STA tBUF
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MB95100B Series
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Parameter SCL clock "L" width SCL clock "H" width Sym- Pin bol name tLOW tHIGH SCL0 SCL0 Conditions Value*2 Min
(2 + nm / 2) tMCLK - 20 (nm / 2) tMCLK - 20
Max
(nm / 2 ) tMCLK + 20
Unit ns ns
Remarks Master mode Master mode Master mode Maximum value is applied when m, n = 1, 8. Otherwise, the minimum value is applied. Master mode Master mode
www..com Start condition
hold time
tHD;STA
SCL0 SDA0
(-1 + nm / 2) tMCLK - 20
(-1 + nm) tMCLK + 20
ns
Stop condition SCL0 tSU;STO setup time SDA0 Start condition SCL0 tSU;STA setup time SDA0 Bus free time between stop condition and start condition tBUF SCL0 SDA0 SCL0 SDA0
R = 1.7 k, C = 50 pF*1
(1 + nm / 2) tMCLK - 20 (1 + nm / 2) tMCLK - 20
(1 + nm / 2) tMCLK + 20 (1 + nm / 2) tMCLK + 20
ns ns
(2 nm + 4) tMCLK - 20
ns
Data hold time tHD;DAT
3 tMCLK - 20
ns
Master mode Master mode When assuming that "L" of SCL is not extended, the minimum value is applied to first bit of continuous data. Otherwise, the maximum value is applied. Minimum value is applied to interrupt at 9th SCL. Maximum value is applied to interrupt at 8th SCL. At reception At reception Undetected when 1 tMCLK is used at reception (Continued)
Data setup time
tSU;DAT
SCL0 SDA0
(-2 + nm / 2) tMCLK - 20 (-1 + nm / 2) tMCLK + 20
ns
Setup time between clearing interrupt and SCL rising SCL clock "L" width SCL clock "H" width
tSU;INT
SCL0
(nm / 2) tMCLK - 20
(1 + nm / 2) tMCLK + 20
ns
tLOW tHIGH
SCL0 SCL0
4 tMCLK - 20 4 tMCLK - 20 2 tMCLK - 20

ns ns ns
Start condition SCL0 tHD;STA detection SDA0
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MB95100B Series
(Continued) Symbol tSU;STO Pin name SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 R = 1.7 k, 1
C = 50 pF*
(VCC = 3.3 V, AVSS = VSS = 0.0 V, TA = -40 C to + 85 C) Conditions Value*2 Min
2 tMCLK - 20
Parameter Stop condition detection Restart condition detection condition
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Max
Unit
Remarks Undetected when 1 tMCLK is used at reception Undetected when 1 tMCLK is used at reception At reception At slave transmission mode At slave transmission mode At reception At reception
ns
tSU;STA
2 tMCLK - 20
ns
Bus free time Data hold time Data setup time Data hold time Data setup time SDASCL (at wakeup function)
tBUF tHD;DAT tSU;DAT tHD;DAT tSU;DAT tWAKEUP
2 tMCLK - 20 2 tMCLK - 20 tLOW - 3 tMCLK - 20 0 tMCLK - 20 Oscillation stabilization wait time + 2 tMCLK - 20

ns ns ns ns ns ns
SCL0 SDA0 SCL0 SDA0 SCL0 SDA0 SCL0 SDA0
*1 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines. *2 : * * * * Refer to " (2) Source Clock/Machine Clock" for tMCLK. m is CS4 bit and CS3 bit (bit 4 and bit 3) of clock control register (ICCR) . n is CS2 bit to CS0 bit (bit 2 to bit 0) of clock control register (ICCR) . Actual timing of I2C is determined by m and n values set by the machine clock (tMCLK) and CS4 to CS0 of ICCR0 register. * Standard-mode : m and n can be set at the range : 0.9 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 0.9 MHz < tMCLK 1 MHz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 MHz < tMCLK 2 MHz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 MHz < tMCLK 4 MHz (m, n) = (1, 98) : 0.9 MHz < tMCLK 10 MHz * Fast-mode : m and n can be set at the range : 3.3 MHz < tMCLK (machine clock) < 10 MHz. Setting of m and n determines the machine clock that can be used below. (m, n) = (1, 8) : 3.3 MHz < tMCLK 4 MHz (m, n) = (1, 22) , (5, 4) : 3.3 MHz < tMCLK 8 MHz (m, n) = (6, 4) : 3.3 MHz < tMCLK 10 MHz
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MB95100B Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics (AVCC = VCC = 1.8 V to 3.3 V [Flash memory product], AVCC = VCC = 1.8 V to 3.6 V [MASK ROM product], AVSS = VSS = 0.0 V, TA = - 40 C to + 85 C) Parameter Resolution Total error
www..com Linearity
Symbol
Value Min - 3.0 Typ Max 10 + 3.0 + 2.5 + 1.9
Unit bit LSB LSB LSB
Remarks
error
- 2.5 - 1.9
Differential linear error
Zero transition voltage
VOT
AVSS - 1.5 LSB AVSS + 0.5 LSB AVSS + 2.5 LSB AVSS - 0.5 LSB AVSS + 1.5 LSB AVSS + 3.5 LSB AVR - 3.5 LSB AVR - 1.5 LSB AVR + 0.5 LSB AVR - 2.5 LSB AVR - 0.5 LSB AVR + 1.5 LSB 1.3 140
V
Flash memory product : 2.7 V AVCC 3.3 V MASK ROM product : 2.7 V AVCC 3.6 V 1.8 V AVCC < 2.7 V Flash memory product : 2.7 V AVCC 3.3 V MASK ROM product : 2.7 V AVCC 3.6 V 1.8 V AVCC < 2.7 V Flash memory product : 2.7 V AVCC 3.3 V MASK ROM product : 2.7 V AVCC 3.6 V 1.8 V AVCC < 2.7 V Flash memory product : 2.7 V AVCC 3.3 V MASK ROM product : 2.7 V AVCC 3.6 V external impedance < at 1.8 k 1.8 V AVCC < 2.7 V external impedance < at 14.8 k
V
Full-scale transition voltage
VFST
V
V s s
Compare time
20
140
0.4 Sampling time
s
30 Analog input current Analog input voltage Reference voltage Reference voltage supply current IAIN VAIN IR IRH -0.3 AVSS AVSS + 1.8
400
+ 0.3 AVR AVCC 600 5
s A V V A A
AVR pin AVR pin, During A/D operation AVR pin, At stop mode
60
MB95100B Series
(2) Notes on Using A/D Converter * About the external impedance of analog input and its sampling time * A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 F to the analog input pin. * Analog input equivalent circuit
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R
Analog input pin
C
Comparator
During sampling : ON 2.7 V AVCC 3.6 V 1.8 V AVCC < 2.7 V Note : The values are reference values. R 1.7 k (Max) 84 k (Max) C 14.5 pF (Max) 25.2 pF (Max)
* The relationship between external impedance and minimum sampling time (External impedance = 0 k to 100 k)
AVCC 2.7 V
100 90 80 70 60 50 40 30 20 10 0 0 5 10 15
(External impedance = 0 k to 20 k)
AVCC 2.7 V
20 18 16 14 12 10 8 6 4 2 0 0 1 2 3 4
External impedance [k]
AVCC 1.8 V
20
25
30
35
40
External impedance [k]
Minimum sampling time [s]
Minimum sampling time [s]
* About errors As |AVR - AVSS| becomes smaller, values of relative errors grow larger.
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MB95100B Series
(3) Definition of A/D Converter Terms * Resolution The level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, analog voltage can be divided into 210 = 1024. * Linearity error (unit : LSB) The deviation between the value along a straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device and the full-scale transition point ("11 1111 1111" "11 1111 1110") compared with the actual conversion values obtained. * Differential linear error (Unit : LSB) Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. www..com * Total error (unit: LSB) Difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise.
Ideal I/O characteristics
VFST
Total error
3FFH 3FEH
3FFH 3FEH 1.5 LSB
Actual conversion characteristic {1 LSB x (N - 1) + 0.5 LSB}
Digital output
Digital output
3FDH
3FDH
004H 003H 002H 001H 0.5 LSB AVSS AVR VOT 1 LSB
004H 003H 002H 001H AVSS AVR VNT Actual conversion characteristic Ideal characteristics
Analog input 1 LSB = AVR - AVSS 1024 (V)
Analog input
Total error of VNT - {1 LSB x (N - 1) + 0.5 LSB} = [LSB] digital output N 1 LSB
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N.
(Continued)
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MB95100B Series
(Continued) Zero transition error
004H
Full-scale transition error
Ideal characteristics
Actual conversion characteristic
3FFH
Digital output
003H
Ideal characteristics Actual conversion characteristic
Digital output
Actual conversion characteristic
3FEH
VFST
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002H
3FDH
(measurement value)
001H
VOT (measurement value)
Actual conversion characteristic
3FCH
AVSS
AVR
AVSS
AVR
Analog input
Analog input
Linearity error
3FFH 3FEH 3FDH
Actual conversion characteristic
Differential linear error
Ideal characteristics
N+1H {1 LSB x N + VOT}
VFST
(measurement value)
Actual conversion characteristic
Digital output
Digital output
V (N+1)T
NH
VNT 004H 003H 002H 001H AVSS
Actual conversion characteristic Ideal characteristics
N-1H
VNT
Actual conversion characteristic
N-2H
VOT (measurement value)
AVR
AVSS
Analog input Linear error in = VNT - {1 LSB x N + VOT} 1 LSB digital output N
Analog input
AVR
Differential linear error = in digital output N
V (N + 1) T - VNT 1 LSB
-1
N : A/D converter digital output value VNT : A voltage at which digital output transits from (N - 1) to N. VOT (Ideal value) = AVSS + 0.5 LSB [V] VFST (Ideal value) = AVR - 1.5 LSB [V]
63
MB95100B Series
6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time (4K bytes sector) Sector erase time (16K bytes sector) Byte programming time
www..com Program/erase
Value Min 10000 2.7 20*3 Typ 0.2*1 0.5*1 32 Max 3.0*2 12.0*2 3600 3.3
Unit s s s cycle V year
Remarks Excludes 00H programming prior erasure. Excludes 00H programming prior erasure. Excludes system-level overhead.
cycle
Power supply voltage at program/erase Flash memory data retention time
Average TA = +85 C
*1 : TA = + 25 C, VCC = 3.0 V, 10000 cycles *2 : TA = + 85 C, VCC = 2.7 V, 10000 cycles *3 : This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at +85 C) .
7. FRAM Program Characteristics
Parameter Read/write cycle* Power supply voltage at read/write Data retention time * : Number of data read/write Value Min 1010 2.7 10 Typ Max 3.6 Unit cycle V year TA = 0 C to +55 C Remarks
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MB95100B Series
MASK OPTION
Part number No. Specifying procedure Clock mode select*1 * Single-system clock mode * Dual-system clock mode FRAM*1 With load of FRAM * Without load of FRAM Low voltage detection reset*2 * With low voltage detection reset * Without low voltage detection reset Clock supervisor*2 * With clock supervisor * Without clock supervisor Selection of oscillation stabilization wait time * Selectable the initial value of main clock oscillation stabilization wait time MB95107B MB95R107B MB95F108BS MB95D108BS MB95F108BW MB95D108BW Setting disabled Dual-system clock mode Specify by part number MB95FV100D-101 Setting disabled Changing by the switch on MCU board No
Specify when Setting disabled ordering MASK Selectable Single-system clock mode Specify by part number
1
www..com 2*
Specify by part number
3
No
No
No
No
4
No Selectable 1 : (22 - 2) /FCH 2 : (212 - 2) /FCH 3 : (213 - 2) /FCH 4 : (214 - 2) /FCH
No
No
No
5
Fixed to oscillation stabilization wait time of (214 - 2) /FCH
Fixed to oscillation stabilization wait time of (214 - 2) /FCH
Fixed to oscillation stabilization wait time of (214 - 2) /FCH
*1 : Refer to table below about clock mode select and load of FRAM. *2 : Low voltage detection reset and clock supervisor are options of 5-V products. Part number MB95107B/R107B MB95F108BS MB95D108BS MB95F108BW MB95D108BW MB95FV100D-101 Clock mode select Single-system Dual-system Single-system Dual-system Single-system Dual-system Load of FRAM No No No Yes No Yes No No
65
MB95100B Series
ORDERING INFORMATION
Part number MB95107BPFV MB95F108BSPFV MB95F108BWPFV MB95R107BPFV MB95D108BSPFV MB95D108BWPFV MB95107BPFM MB95F108BSPFM www..com MB95F108BWPFM MB95R107BPFM MB95D108BSPFM MB95D108BWPFM MB2146-301A (MB95FV100D-101PBT) Package
64-pin plastic LQFP (FPT-64P-M03)
64-pin plastic LQFP (FPT-64P-M09)
(
MCU board 224-pin plastic PFBGA (BGA-224P-M08)
)
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MB95100B Series
PACKAGE DIMENSIONS
64-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 10.0 x 10.0 mm Gullwing Plastic mold 1.70 mm MAX 0.32g P-LFQFP64-10x10-0.50
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(FPT-64P-M03)
Code (Reference)
64-pin plastic LQFP (FPT-64P-M03)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
12.000.20(.472.008)SQ
* 10.000.10(.394.004)SQ
48 33
0.1450.055 (.006.002)
49
32
Details of "A" part 0.08(.003) 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
64 17
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.25(.010)
LEAD No.
1
16
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F64009S-c-5-8
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html (Continued)
67
MB95100B Series
(Continued)
64-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 12 x 12 mm Gullwing Plastic mold 1.70 mm MAX P-LQFP64-12x12-0.65
www..com
(FPT-64P-M09)
64-pin plastic LQFP (FPT-64P-M09)
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
14.000.20(.551.008)SQ
* 12.000.10(.472.004)SQ
48 33
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
C
2003 FUJITSU LIMITED F64018S-c-3-5
Dimensions in mm (inches). Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
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MB95100B Series
The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. www..com The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept.
F0612

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